1. Field of the Invention
The present invention relates to a vertical double diffused MOSFET (referred to at VDMOSFET hereinafter) constituting a power semiconductor device and, particularly, to a low breakdown voltage VDMOSFET.
2. Description of the Prior Art
Instead of bipolar transistor, a MOSFET has been used as an element constituting a power semiconductor device in view of a merit of higher switching speed. Among DSAMOSFET known as such MOSFET, the VDMOSFET has been used mainly in view of easiness of fabrication.
Such conventional VDMOSFET is usually manufactured as follow: An N.sup.- type epitaxial layer having a predetermined thickness is formed on one surface of an N.sup.+ type silicon substrate and, on the N.sup.- type epitaxial layer, a gate oxide film having a predetermined thickness and a gate electrode comprising an N.sup.+ type polycrystalline silicon film having a predetermined thickness are formed. The gate electrode (and the gate oxide film) is formed with a plurality of predetermined polygonal open windows at regularly arranged positions. On a surface of the N.sup.- type epitaxial layer exposed in each open window, a P.sup.+ type base region self-aligned with the open window, that is, with an edge portion of the gate electrode, and an N.sup.+ type source region having one end self-aligned with the edge portion of the gate electrode are formed. That is, one VDMOSFET is provided in each open window. Although the VDMOSFETs have associated P.sup.+ type base regions and N.sup.+ type source regions, respectively, their gate electrodes are common. The P.sup.+ type base region of each VDTMOSFET is exposed in a central portion of the open window. That is, the N.sup.+ type source region formed on the P.sup.+ type base region is provided not on the whole area of the open window but on an inner peripheral portion of the open window with an outer edge thereof being self-aligned with the edge of the open window and an inner edge thereof being at a predetermined distance measured from the edge portion of the open window.
An inter-layer insulating film covering the gate electrode including the open windows is provided in which contact-holes deep enough to reach the P.sup.+ type base regions and N.sup.+ type source regions in the windows are formed, respectively. On the inter-layer insulating films, a source electrode is formed so that is connects the P.sup.+ type base regions and N.sup.+ type source regions of all of the VDMOSFETs through the contact holes. N type drain regions of these VDMOSFETs are common and formed by the N.sup.- type epitaxial layer and the N.sup.+ type silicon substrate. A drain electrode is formed on the other surface of the N.sup.+ type silicon substrate. Thus, the power semiconductor device constituted as mentioned above includes VDMOSFETs connected in parallel, the number thereof corresponding to that of the open windows.
Junction depth of the P.sup.+ type base region is X.sub.jb in vertical direction and that of a portion thereof extending from the edge portion of the gate electrode to a portion immediately below the gate electrode is X.sub.jb,l (which is nearly equal to 0.8 X.sub.jb) in horizontal direction. Vertical junction depth of the N.sup.+ type source region is X.sub.js (&lt;X.sub.jb) and that of a portion extending from the edge portion of the gate electrode to a portion thereof immediately below the gate electrode is X.sub.js,l (which is nearly equal to 0.8 X.sub.js) in horizontal direction. A portion of the P.sup.+ type base region which is directly in contact with the gate oxide film immediately below the gate electrode is a channel region of the associated VDMOSFET. Channel length is substantially equal to (X.sub.jb,l -X.sub.js,l). When a minimum distance between two adjacent opening windows is equal to a gate electrode length L.sub.G and L.sub.G &gt;2 X.sub.jb,l, a plurality of VDMOSFETs are formed below a gate electrode.
The opening window may be regular square or regular hexagonal. For square opening windows having desired side length, their centers are arranged at intersections of a two dimensional lattice having a desired lattice interval as disclosed in, for example, Japanese Patent Application Laid-open No. Sho 52-132684 (publication date: Nov. 7, 1977). Four sides of each square opening window are parallel to the square lattice. As a modification of the square opening window, an octagonal window is disclosed in U.S. Pat. No. 5,016,066, (issued on May 14, 1991 and assigned to the assignee of this application). A right hexagonal window is disclosed in, for example, U.S. Pat. No. 5,008,725 (issued on Apr. 16, 1991). One of objects of the right hexagonal window is to arrange the windows in a close-packed state. Since both U.S. Pat. Nos. 5,016,066 and 5,008,725 relate to VDMOSFET's having high BVdss which is breakdown voltage between a drain and source regions when the source region and a base region are short-circuited, impurity density distribution in the drain region immediately below a gate electrode is considered.
On-resistance is one of important characteristics of a VDMOSFET. If on-resistance is low, a switching speed and current density of a power semiconductor device become high, respectively. As disclosed in IEEE Transactions of Electron Devices, Vol. ED-27, No. 2, pp. 356-367, 1980, on-resistance R.sub.ON in a VDMOSFET is represented by EQU R.sub.ON =R.sub.E +R.sub.D +R.sub.JFET +R.sub.SUB
where contact resistance between a source region and a source electrode, etc., are neglected and where R.sub.E is on-resistance in a channel region of the VDMOSFET (in enhanced mode), R.sub.D is on-resistance in an accumulation layer (depletion mode from the view of MOSFET) of a drain region (epitaxial layer) immediately below a gate electrode, R.sub.JFET is on-resistance in a JFET region and R.sub.SUB is on-resistance of the epitaxial layer and a silicon substrate excluding the JFET region.
In a VDMOSFET having high breakdown voltage, it is necessary, in order to obtain high BV.sub.DSS, to make the epitaxial film thick, to make impurity density of the epitaxial layer low and to make X.sub.jb of a base region large. Therefore, R.sub.ON of the high breakdown voltage VDMOSFET mainly depends on R.sub.D +R.sub.JFET +R.sub.SUB rather than R.sub.E.
On the other hand, for a low breakdown voltage VDMOSFET, it is possible to reduce thickness of an epitaxial layer, impurity density thereof and X.sub.jb of a base region. Therefore, R.sub.ON of such VDMOSFET depends largely on R.sub.E. In order to reduce R.sub.ON, it is enough to make a channel length short and a channel width large since R is proportional to (channel length)/(channel width). The channel length is restricted by the punch-through characteristics. Therefore, in order to further reduce R.sub.ON of a VDMOSFET, the channel width should be made as large as possible. In view of the power semiconductor device, it is important to reduce on-resistance (normalized-R.sub.ON) per unit area of the power semiconductor device. Assuming an area to be occupied by a single low breakdown voltage VDMOSFET, that is, a cell size, as A.sub.C, the number of VDMOSFETs per unit area is 1/A.sub.C. That is, 1/A.sub.C VDMOSFETs are connected in parallel within the unit area. Therefore, normalized-R.sub.ON =A.sub.C .multidot.R.sub.ON must be small. In other words, the channel width per unit area must be made large.
To make a channel width per unit area large when polygonal opening windows having conventional construction and regularly arranged on a gate electrode are provided, with channel length of each VDMOSFET and X.sub.jb of a base region thereof, etc., being constant, is to provide right hexagonal opening windows such as shown in U.S. Pat. No. 5,016,066 on the gate electrode, in which case, on-resistance (A.sub.C .multidot.R.sub.ON) per unit area becomes minimum. That is, in the conventional VDMOSFET, it is impossible to further reduce A.sub.C .multidot.R.sub.ON. Therefore, when a power semiconductor device is constituted with conventional low breakdown voltage VDMOSFETs, it is difficult to further improve switching speed and current density of the power semiconductor device.